1. Field of the Invention
The present invention generally relates to a semiconductor memory device and, more particularly, to a pair of adjacent common complementary data lines, namely the wiring between a pair of global I/O lines.
2. Description of Prior Art
Referring to FIG. 12, there is shown a circuit diagram (for a reading operation in this case) illustrating a memory array of a conventional semiconductor memory device and its peripheral circuits. In the drawing, reference numerals 11 through 14 denote memory cell transistors, reference numerals 15 through 20 denote switching transistors for row decoding, reference numerals 21 and 22 denote output transistors (main amplifiers), reference numerals 23 through 26 denote memory cell capacitors, reference numerals 27 and 28 denote sense amplifiers, reference numeral 29 denotes an output preamplifier, reference symbols BL1 and BL2 denote bit lines, reference symbols ZBL1 and ZBL2 denote bit bar lines, reference symbol GIO denotes a global I/O line, reference symbol ZGIO denotes a global I/O bar line, and reference symbols WL0 and WL1 denote word lines. The BL1 and the ZBL1 are paired and the BL2 and the ZBL2 are paired. The GIO and the ZGIO are paired in global I/O line. The switch transistors 15 through 20 constitute selector switches.
The following describes the operation of the above-mentioned conventional semiconductor memory device.
A bit line selected at reading a device using a memory cell of one-transistor type such as shown in FIG. 12 is connected one of the pair of global I/O lines through the row decoder switching transistors 15 to 20. At this moment, because the common data I/O line possibly gives a noise to the bit line pair, the row decoder starts operating after the sense amplifiers 27 and 28 detect an infinitesimal signal and amplifies the detected signal. Information read from the bit line is supplied to the global I/O line pair connected by the switch transistors 15 through 20, the supplied information is amplified by the output preamplifier 29, and the amplified information is transmitted by the output transistors (main amplifiers) 21 and 22.
Referring to FIG. 13, there is shown a plan view illustrating the common complementary data pair namely the global I/O line pair of the conventional semiconductor memory device. Referring to FIG. 14, there is shown a cross section of the wiring layer of FIG. 13 along line 14--14. In the drawing, reference numeral 4 denotes a semiconductor substrate, reference numeral 5 denotes an insulation layer such as a field oxide film, and reference symbols GIO(n) and ZGIO(n) denote a global I/O line (n) and a global I/O bar line (n) respectively which constitute a global I/O line pair (n) (n being a natural number). If one of the GIO(n) and the ZGIO(n) is a bit line, the other is a bit bar line. Namely, a GIO(1) and a ZGIO(1) constitute a global I/O pair (1) and a GIO(2) and a ZGIO(2) constitute a global I/O line pair (2).
In the conventional example, a single wiring layer is used for the bit line and the bit bar line of the global I/O line pair (n) as shown in FIGS. 13 and 14. This global I/O line pair (n) is connected via a selector switch for selecting one of a plurality of bit lines to be connected to a plurality of memory cells.
Referring to FIG. 15, there is shown a diagram illustrating the coupling capacitors between wirings of the bit line GIO(1) and the bit bar line ZGIO(1) of the global I/O line pair (1) and the bit line GIO(2) and the bit bar line ZGIO(2) of the global I/O line pair (2). In the drawing, C101 denotes the coupling capacitor between the bit line GIO(1) and the bit bar line ZGIO(1), C102 denotes the coupling capacitor between the bit bar line ZGIO(1) and the bit line GIO(2), and C103 denotes the coupling capacitor between the bit line GIO(2) and the bit bar line ZGIO(2).
Referring to FIG. 16, there is shown a diagram illustrating an influence of the coupling capacitor C102 between the bit bar line of the global I/O line pair (1) and the bit line of the global I/O line pair (2) shown in FIG. 15 to be given to the potential of the bit bar line of the global I/O line pair (1) relative to the potential variation of the bit line of the global I/O line pair (2).
The following describes the operation of the above-mentioned conventional constitution.
The bit bar line ZGIO(1) of the global I/O line pair has the coupling capacitor C102 with the bit line GIO(2) of the global I/O line pair (2). When the potential of the bit line GIO(2) of the global I/O line pair (2) changes, the bit bar line ZGIO(1) of the global I/O line pair (1) is influenced by the rise (at changing of the bit line potential of the global I/O line pair (2) from low to high) and the fall (at changing of the bit line potential of the global I/O line pair (2) from high to low) in the bit line potential of the global I/O line pair (2) by the coupling capacitor between the bit lines. This influence interferes with the operation of the bit bar line ZGIO(1) of the global I/O line pair (1). This holds true with the influence to be given by the potential change of the bit bar line ZGIO(1) of the global I/O line pair (1) to the bit line potential of the global I/O line pair (2).
Therefore, in order to protect the bit bar line ZGIO(1) of the global I/O line pair (1) from being influenced by the bit line GIO(2) of the global I/O line pair (2) and the bit line GIO(2) of the global I/O line pair (2) from being influenced by the bit bar line ZGIO(1) of the global I/O line pair (1), the wiring pitch between the bit line GIO(n) and the bit bar line ZGIO(n) must be widened. However, if the wiring pitch is widened, it prevents the efficiency of wiring area from being enhanced, which imposes a problem to the future trend of narrower wiring pitches required by ever higher device integration.